Power MOS devices, including laterally diffused metal-oxide-semiconductor (LDMOS) devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. In conventional LDMOS devices, which typically include an LDD region, the LDD region is often formed at or near an upper surface interface between the silicon and oxide of the device. Locating the LDD region in close relative proximity to the silicon/oxide interface, however, significantly increases the likelihood that ionized carriers will become trapped at the interface, thereby resulting in undesirable hot carrier degradation (HCD) in the device.
HCD in an MOS device generally results from heating and subsequent injection of carriers into the gate oxide of the device, which results in a localized and nonuniform buildup of interface states and oxide charges near and underneath a gate of the device. This phenomenon can produce variations in certain characteristics of the MOS device, including threshold voltage, transconductance, drain current, etc., thus undesirably affecting the operation and reliability of the device. It is well known that HCD is a strong function of the internal electric field distributions at the interface of the MOS device.
In many applications, such as, for example, power applications and applications in which high-frequency operation is desired, such as in a radio frequency (RF) range (e.g., above 1 gigahertz (GHz)), it is desirable to minimize the on-resistance, RON, associated with the MOS device. In an LDMOS device, since the on-resistance is dominated primarily by the characteristics of the LDD region, one known methodology for reducing the on-resistance is to increase the doping concentration of the LDD region. However, since the LDD region is typically formed at the silicon/oxide interface of the device, increasing the doping concentration of the LDD region also undesirably increases HCD in the device.
Other attempts at reducing the on-resistance of the MOS device have included increasing the junction depth of the LDD region. However, since the gate-to-drain capacitance, Cgd, of the device is generally proportional to the junction depth of the LDD region, as the depth of the LDD region increases the gate-to-drain capacitance also increases, thereby undesirably affecting the high-frequency performance of the device. Thus, prior attempts to improve the high-frequency performance of the MOS device have primarily focused on optimizing a trade-off between on-resistance, HCD and gate-to-drain capacitance in the device.
Conventional methodologies for reducing the on-resistance of the LDMOS device without significantly increasing HCD and/or the gate-to-drain capacitance in the device have generally been unsuccessful thus far. Accordingly, it would be desirable to form an MOS device exhibiting improved on-resistance characteristics without significantly increasing HCD or impacting the high-frequency performance of the device.